As semiconductor processes continue to scale downwards, e.g., shrink, the desired spacing between features or pitch also becomes smaller. To this end, in the smaller technology nodes it becomes ever more difficult to fabricate front end of line (FEOL), back end of line (BEOL) and middle of line (MOL) features due to the critical dimension (CD) scaling and process capabilities.
For example, as the geometry of devices continuously shrinks, the influence of line edge roughness (LER) and line width roughness (LWR) on device performance becomes more and more significant. As an example, a relatively high LER can lead to degradation and poor fill capabilities, resulting in challenges for integrating certain materials and processes.